Computer storage systems (such as optical, magnetic, and the like) record digital data onto the surface of a storage medium, which is typically in the form of a rotating magnetic or optical disk, by altering a surface characteristic of the disk. The digital data serves to modulate the operation of a write transducer (write head) which records binary sequences onto the disk at a predetermined baud rate in radially concentric or spiral tracks. In magnetic recording systems, for example, the digital data modulates the current in a write coil in order to record a series of magnetic flux transitions onto the surface of a magnetizable disk. And in optical recording systems, for example, the digital data may modulate the intensity of a laser beam in order to record a series of "pits" onto the surface of an optical disk. When reading this recorded data, a read transducer (read head), positioned in close proximity to the rotating disk, senses the alterations on the medium and generates a sequence of corresponding pulses in an analog read signal. These pulses are then detected and decoded by read channel circuitry in order to reproduce the digital sequence.
Detecting and decoding the pulses into a digital sequence can be performed by a simple peak detector in a conventional analog read channel or, as in more recent designs, by a discrete-time sequence detector in a sampled amplitude read channel. Discrete-time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interference (ISI) and are less susceptible to channel noise. Consequently, discrete-time sequence detectors increase the capacity and reliability of the storage system.
There are several well known discrete-time sequence detection methods including discrete-time pulse detection (DPD), partial response (PR) with Viterbi detection, maximum likelihood sequence detection (MLSD), decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF).
In a conventional peak detection read channel, analog circuitry detects peaks in the continuous time analog read signal generated by the read head. The analog read signal is "segmented" into bit cell periods and interpreted during these segments of time. A peak detected during a bit cell period may represent a binary "1" bit, whereas the absence of a peak may represent a binary "0" bit. Errors in detection occur when the bit cells are not correctly aligned with the analog pulse data. To this end, timing recovery in the read channel adjusts the bit cell periods so that the peaks occur in the center of the bit cells on average in order to minimize detection errors. Since timing information is derived only when peaks are detected, the input data stream is normally run-length limited (RLL) to limit the number of consecutive "0" bits.
As the pulses are packed closer together on the data tracks in the effort to increase data density, detection errors can also occur due to intersymbol interference (ISI), a distortion in the read signal caused by closely spaced, overlapping pulses. This interference can cause a peak to shift out of its bit cell, or decrease the magnitude of the peak, resulting in a detection error. This ISI effect is reduced by decreasing the data density or by employing an encoding scheme that ensures a minimum number of "0" bits occur between "1" bits. For example, a (d,k) run-length limited (RLL) code constrains to d the minimum number of "0" bits between "1" bits, and to k the maximum number of consecutive "0" bits. A typical (1,7) RLL 2/3 rate code encodes 8 bit data words into 12 bit codewords to satisfy the (1,7) constraint.
Sampled amplitude detection, such as partial response (PR) with Viterbi detection, allows for increased data density by compensating for intersymbol interference and the effect of channel noise. Unlike conventional peak detection systems, sampled amplitude recording detects digital data by interpreting, at discrete time instances, the actual value of the pulse data. To this end, the read channel comprises a sampling device for sampling the analog read signal, and a timing recovery circuit for synchronizing the samples to the baud rate (code bit rate). Before sampling the pulses, a variable gain amplifier (VGA) adjusts the read signal's amplitude to a nominal value consistent with the desired partial response and within the optimum operating range of the sampling device. A low pass analog filter filters the read signal at the output of the VGA to attenuate channel and aliasing noise. After sampling, a discrete equalizer equalizes the sample values according to a desired partial response, and a discrete-time sequence detector, such as a Viterbi detector, interprets the equalized sample values in context to determine a most likely sequence for the recorded digital data (i.e., maximum likelihood sequence detection (MLSD)). MLSD takes into account the effect of ISI and channel noise in the detection algorithm, thereby decreasing the probability of a detection error. This increases the effective signal to noise ratio and, for a given (d,k) constraint, allows for significantly higher data density as compared to conventional analog peak detection read channels.
The application of sampled amplitude techniques to digital communication channels is well documented. See Y. Kabal and S. Pasupathy, "Partial Response Signaling", IEEE Trans. Commun. Tech., Vol. COM-23, pp.921-934, September 1975; and Edward A. Lee and David G. Messerschmitt, "Digital Communication", Kluwer Academic Publishers, Boston, 1990; and G. D. Forney, Jr., "The Viterbi Algorithm", Proc. IEEE, Vol. 61, pp. 268-278, March 1973.
Applying sampled amplitude techniques to magnetic storage systems is also well documented. See Roy D. Cideciyan, Francois Dolivo, Walter Hirt, and Wolfgang Schott, "A PRML System for Digital Magnetic Recording", IEEE Journal on Selected Areas in Communications, Vol. 10 No. 1, January 1992, pp.38-56; and Wood et al, "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel", IEEE Trans. Commun., Vol. Com-34, No. 5, pp. 454-461, May 1986; and Coker Et al, "Implementation of PRML in a Rigid Disk Drive", IEEE Trans. on Magnetics, Vol. 27, No. 6, Nov. 1991; and Carley et al, "Adaptive Continous-Time Equalization Followed By FDTS/DF Sequence Detection", Digest of The Magnetic Recording Conference, Aug. 15-17, 1994, pp. C3; and Moon et al, "Constrained-Complexity Equalizer Design for Fixed Delay Tree Search with Decision Feedback", IEEE Trans. on Magnetics, Vol. 30, No. 5, September 1994; and Abbott et al, "Timing Recovery For Adaptive Decision Feedback Equalization of The Magnetic Storage Channel", Globecom'90 IEEE Global Telecommunications Conference 1990, San Diego, Calif., November 1990, pp.1794-1799; and Abbott et al, "Performance of Digital Magnetic Recording with Equalization and Offtrack Interference", IEEE Transactions on Magnetics, Vol. 27, No. 1, January 1991; and Cioffi et al, "Adaptive Equalization in Magnetic-Disk Storage Channels", IEEE Communication Magazine, February 1990; and Roger Wood, "Enhanced Decision Feedback Equalization", Intermag'90.
The principles disclosed herein are applicable regardless as to the particular discrete-time sequence detection method employed. The present invention applies to the above-identified sequence detection methods as well as others not mentioned, and even future techniques.
Similar to conventional peak detection systems, sampled amplitude detection requires timing recovery in order to correctly extract the digital sequence. Rather than process the continuous signal to align peaks to the center of bit cell periods as in peak detection systems, sampled amplitude systems synchronize the pulse samples to the baud rate. In conventional sampled amplitude read channels, timing recovery synchronizes a sampling clock by minimizing an error between the signal sample values and estimated sample values. A pulse detector or slicer determines the estimated sample values from the read signal samples. Even in the presence of ISI the sample values can be estimated and, together with the signal sample values, used to synchronize the sampling of the analog pulses in a decision-directed feedback system.
A phase-locked-loop (PLL) normally implements the timing recovery decision-directed feedback system. The PLL comprises a phase detector for generating a phase error estimate based on the difference between the estimated samples and the read signal samples. A PLL loop filter filters the phase error, and the filtered phase error operates to synchronize the channel samples to the baud rate.
Conventionally, the phase error adjusts the frequency of a sampling clock which is typically the output of a variable frequency oscillator (VFO). The output of the VFO controls a sampling device, such as an analog-to-digital (A/D) converter, to synchronize the sampling to the baud rate.
Similar to timing recovery, the gain control loop in sampled amplitude read channels is implemented as a decision-directed feed back system. The gain control loop comprises a gain error detector for generating a gain error based on the difference between the estimated samples and the read signal samples. A loop filter filters the gain error, and the filtered gain error controls the operation of the VGA to adjust the amplitude of the analog read signal until it is consistent with the desired partial response and within the optimum operating range of the sampling device.
A periodic sequence of bits referred to as an acquisition preamble is normally recorded immediately preceding the user data in a sector to allow the gain control and timing recovery loops to "pull-in" to the desired amplitude and to synchronize to the correct frequency and phase of the baud rate. It is desirable to minimize the required length of the acquisition preamble in order to reserve more area on the disk for recording user data. This means minimizing the transport delay in the timing recovery and gain control loops during acquisition to allow for an increase in bandwidth and enable faster "pull-in" times. In prior art sampled amplitude read channels, the transport delay is minimized by removing the discrete equalizer filter from the data path during acquisition. The additional equalization provided by the discrete equalizer is not necessary because the acquisition preamble is substantially a single tone. After acquisition, the discrete equalizer is switched back into the data path in order to read (i.e., track) the random user data.
Although the above technique decreases the acquisition time and the length of the acquisition preamble, the transport delay due to the discrete equalizer still degrades the performance of timing recovery when tracking the user data. Thus, the complexity (order) of the discrete equalizer is typically limited in prior art read channels to minimize the transport delay in the timing recovery loop. The conventional synchronous-sampling timing recovery is also adversely affected by variations in the fabrication process of the analog components, such as the VFO, as well as changes in the operating characteristics of the recording system, such as temperature drift.
The above-referenced co-pending patent application entitled "A Sampled Amplitude Read Channel Employing Interpolated Timing Recovery" discloses a wholly digital timing recovery loop wherein the analog read signal is sampled asynchronously and the asynchronous sample values interpolated to generate the sample values synchronized to the baud rate. This method of timing recovery removes the delay associated with the discrete equalizer from the loop for both acquisition and tracking, which allows for a more complex discrete equalizer. Furthermore, interpolated timing recovery is not affected by process variations or changes in operating characteristics because there are no analog components. However, the prior art method for generating the gain error requires sample values that are synchronized to the baud rate. This means the gain control loop must operate on the interpolated sample values at the output of timing recovery which introduces a significant transport delay during acquisition due to the delay associated with the interpolation filter in the timing recovery circuit.
There is, therefore, a need for an improved gain control loop in a sampled amplitude read channel employing interpolated timing recovery. In particular, an object of the present invention is to avoid the delay associated with the discrete equalizer filter and the timing recovery interpolation filter in order to minimize the acquisition time and the corresponding length of the acquisition preamble.